Pdf in this paper, effects preceding a latchup fault in insulated gate bipolar transistors igbts are studied as they manifest. This application note explains how this occurs and what can be done to prevent it for mosfet drivers. A latchup is a type of short circuit which can occur in an integrated circuit ic. Latchup of parasitic thyristor in igbt insulated gate. A latch up is a type of short circuit which can occur in an integrated circuit ic. Low driving power and a simple drive circuit due to the input mos gate structure. When igbt is turned off, the mosfet portion of the device turns off quite rapidly, and the portion of the total device current that it carries goes to zero. The mc33153 is specifically designed as an igbt driver for high power applications that include ac induction motor control, brushless dc motor control and uninterruptable power supplies.
Figure 5 shows that the maximum static saturation current is around 4000acm2 with no latch up occurring. An6076 design and application guide of bootstrap circuit for high. Figure 7 shows latchup case that the highside output does not changed by input. Dynamic avalanche behavior of power mosfets and igbts under unclamped inductive switching conditions. The individual bipolar devices have low current gain, with a. In particular, for the dynamic latch up characteristics shown in figure 6, the proposed fs igbt. Turnoff time as a precursor for gate bipolar transistor latchup. Thus, although the latchup effect is no longer a problem with modern cmos circuits. The first circuit shows an nchannel power mosfet driving a wide base pnp.
When a customer buys an integrated circuit a gate or an operational. Unfortunately, under dynamic conditions when the igbt is switching from on to off, it may latch up at drain current values less than the static current value. The p substrate and n drift and p body regions form the pnp transistor. A possibility for a latchup mitigation is the latchup protection technology circuit. On the other hand, with the increasing cells density and speed of newer technology, dynamic latchup might affect high current applications. It supports most of the voltage and allows the mosfet to be a low voltage type and consequently have a low rdson value. Can someone help us with latching issues when driving igbts. Catastrophic failure and fault9tolerant design of igbt power. The dynamic latch up process in conventional and modified lateral insulated gate bipolar transistor ligbt structures is studied in this paper. In the first faulttolerant motor drive reported by janhs. Pdf dynamic avalanche behavior of power mosfets and. Catastrophic failure and faulttolerant design of igbt. Latch up an igbt is made of four alternate pnpn layers. The series resistance of the gate drive circuit limits this current.
Latchup is a failure mode where the igbt can no longer be turned off by the gate. A circuit symbol for the igbt is shown in figure 3. When the same set up is tested on a resistive load no latch up is noticed. Scr parasitic structure is formed as a part of the totempole pmos and nmos transistor pair on the output drivers of the gates. Opencircuit can also be due to absence of gate drive signal.
Insulated gate bipolar transistor igbt basics ixys corporation. The bootstrap circuit is useful in a highvoltage gate driver and operates as. The first circuit shows an nchannel power mosfet driving a wide. More specifically it is the inadvertent creation of a lowimpedance path between the.
Consider the igbt embedded in a stepdown converter circuit. The latchup does not have to happen between the power rails it can happen at any place where the required parasitic structure exists. Static latchup happens at high collector currents, which turn on the parasitic npn. Robust design with major power discrete technologies. The jfet represents the constriction of current between any two neighboring igbt cells. Most cmos ics, given proper conditions, can latch like an scr, creating a short circuit from the positive supply voltage to ground. White paper fourthgeneration field stop igbt with high. More specifically it is the inadvertent creation of a lowimpedance path between the power supply rails of a mosfet circuit. In a previous study, we have argued that the modified structure shows a superior static latch up performance at high operating temperatures. A nearly native igbt model would be a worthwhile addition to ltspice. Catastrophic failure and faulttolerant design of igbt power electronic convertersan overview. When a latchup is detected, the lpt circuit shuts down the chip and holds it powereddown for a preset time.
The latch up immunity was evaluated under static and dynamic conditions, as shown in figures 5 and 6 respectively. Primary failure modes associated with igbt latchup faults are. How the igbt insulated gate bipolar transistor latch up. Its simple, fast and seems to be a reasonable match to. Dynamic latchup in advanced ligbt structures at high.
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